`timescale 1ns / 1ps
/*--------------------------------------------------------------------*\
FileName        : cbb_synclk_switch.v
Author          ：hpy
Email           ：yuan_hp@qq.com
Date            ：2025年05月14日
Description     ：同步时钟切换模块,消除毛刺

1.例化
cbb_synclk_switch u1 ( 
    .i_clk1(),
    .i_clk2(),
    .i_rst_n(),
    .i_sel(),  //时钟选择  1: output i_clk2 ,0: output i_clk1
    .o_clk()  //时钟输出
);

\*--------------------------------------------------------------------*/

module cbb_synclk_switch(

input                                   i_clk1,
input                                   i_clk2,
input                                   i_rst_n,
input                                   i_sel,
output                                  o_clk 
);

reg ff1,ff1_d;
reg ff2,ff2_d;

always @(negedge i_clk1 or negedge i_rst_n) begin
    if(!i_rst_n)  {ff1,ff1_d} <= 2'b00;
    else begin
        ff1_d <= ~ff2 & i_sel;
        ff1 <= ff1_d;
      end
    end
always @(negedge i_clk2 or negedge i_rst_n) begin
    if(!i_rst_n) {ff2,ff2_d} <= 2'b00;
    else begin
        ff2_d <= ~ff1 & ~i_sel;
        ff2 <= ff2_d;        
      end
    end

assign o_clk = (ff1 & i_clk1) | (ff2 & i_clk2); 


endmodule
 
